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Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl |
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Date: |
Fri, 15 Oct 2021 15:05:52 +1000 |
On Thu, Oct 14, 2021 at 6:54 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Shortly, the set of supported XL will not be just 32 and 64,
> and representing that properly using the enumeration will be
> imperative.
>
> Two places, booting and gdb, intentionally use misa_mxl_max
> to emphasize the use of the reset value of misa.mxl, and not
> the current cpu state.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 9 ++++++++-
> hw/riscv/boot.c | 2 +-
> semihosting/arm-compat-semi.c | 2 +-
> target/riscv/cpu.c | 24 ++++++++++++++----------
> target/riscv/cpu_helper.c | 12 ++++++------
> target/riscv/csr.c | 24 ++++++++++++------------
> target/riscv/gdbstub.c | 2 +-
> target/riscv/monitor.c | 4 ++--
> 8 files changed, 45 insertions(+), 34 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e708fcc168..87248b562a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1)
> FIELD(TB_FLAGS, HLSX, 9, 1)
> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
>
> -bool riscv_cpu_is_32bit(CPURISCVState *env);
> +#ifdef CONFIG_RISCV32
Besides the typo:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
- [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/13
- [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/13
- [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/13
- [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/13
- [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/13
- [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/13
- [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/13
- [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/13
- [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/13
- [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/13