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Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 |
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Date: |
Fri, 15 Oct 2021 15:08:03 +1000 |
On Thu, Oct 14, 2021 at 6:57 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use the same REQUIRE_64BIT check that we use elsewhere,
> rather than open-coding the use of is_32bit.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index fa451938f1..bbc5c93ef1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
>
> static bool amo_check64(DisasContext *s, arg_rwdvm* a)
> {
> - return !is_32bit(s) && amo_check(s, a);
> + REQUIRE_64BIT(s);
> + return amo_check(s, a);
> }
>
> GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
> --
> 2.25.1
>
>
- [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, (continued)
- [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/13
- [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/13
- [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/13
- [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/13
- [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/13
- [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/13
- [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/13
- [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/13