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Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op |
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Date: |
Fri, 15 Oct 2021 15:09:53 +1000 |
On Thu, Oct 14, 2021 at 6:55 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We're currently assuming SEW <= 3, and the "else" from
> the SEW == 3 must be less. Use a switch and explicitly
> bound both SEW and SEQ for all cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index bbc5c93ef1..91fca4a2d1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a,
> uint8_t seq)
> gen_helper_exit_atomic(cpu_env);
> s->base.is_jmp = DISAS_NORETURN;
> return true;
> - } else {
> - if (s->sew == 3) {
> - if (!is_32bit(s)) {
> - fn = fnsd[seq];
> - } else {
> - /* Check done in amo_check(). */
> - g_assert_not_reached();
> - }
> - } else {
> - assert(seq < ARRAY_SIZE(fnsw));
> - fn = fnsw[seq];
> - }
> + }
> +
> + switch (s->sew) {
> + case 0 ... 2:
> + assert(seq < ARRAY_SIZE(fnsw));
> + fn = fnsw[seq];
> + break;
> + case 3:
> + /* XLEN check done in amo_check(). */
> + assert(seq < ARRAY_SIZE(fnsd));
> + fn = fnsd[seq];
> + break;
> + default:
> + g_assert_not_reached();
> }
>
> data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
> --
> 2.25.1
>
>
- Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, (continued)
- [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/13
- [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/13
- [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/13
- [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/13
- [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/13
- [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/13
- Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Alistair Francis, 2021/10/15
- [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/13