Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo

qemu-riscv

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Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64

From:	LIU Zhiwei
Subject:	Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
Date:	Thu, 14 Oct 2021 13:54:32 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0


On 2021/10/14 上午4:50, Richard Henderson wrote:

Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>

Zhiwei

---
  target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1..bbc5c93ef1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)

static bool amo_check64(DisasContext *s, arg_rwdvm* a)

  {
-    return !is_32bit(s) && amo_check(s, a);
+    REQUIRE_64BIT(s);
+    return amo_check(s, a);
  }

GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)

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[PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration, (continued)
- [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/13
- [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, LIU Zhiwei, 2021/10/14
    - Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/14
  - Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/15
- [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, LIU Zhiwei, 2021/10/14
    - Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/14
  - Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Alistair Francis, 2021/10/15
- [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, LIU Zhiwei <=
  - Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Alistair Francis, 2021/10/15
- [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, LIU Zhiwei, 2021/10/14
    - Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/14
  - Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/15
- [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/13
- [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/13
- [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, LIU Zhiwei, 2021/10/14
  - Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Alistair Francis, 2021/10/15

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