Re: [PATCH v4 12/20] target/riscv: Split out the vill from vtype

[Alistair Francis]

On Fri, Nov 12, 2021 at 2:03 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> We need not specially process vtype when XLEN changes.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h           |  1 +
>  target/riscv/cpu_helper.c    |  3 +--
>  target/riscv/csr.c           | 13 ++++++++++++-
>  target/riscv/machine.c       |  5 +++--
>  target/riscv/vector_helper.c |  3 ++-
>  5 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9fba876e08..52ce670cbe 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -119,6 +119,7 @@ struct CPURISCVState {
>      target_ulong vl;
>      target_ulong vstart;
>      target_ulong vtype;
> +    bool vill;
>
>      target_ulong pc;
>      target_ulong load_res;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index a40ed6d748..9b9dc83ab9 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -78,8 +78,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
> *pc,
>      if (riscv_has_ext(env, RVV)) {
>          uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
>          bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
> -                    FIELD_EX64(env->vtype, VTYPE, VILL));
> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
>          flags = FIELD_DP32(flags, TB_FLAGS, SEW,
>                      FIELD_EX64(env->vtype, VTYPE, VSEW));
>          flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6bb2d09519..8f8f170768 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -286,7 +286,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int 
> csrno,
>  static RISCVException read_vtype(CPURISCVState *env, int csrno,
>                                   target_ulong *val)
>  {
> -    *val = env->vtype;
> +    uint64_t vill;
> +    switch (cpu_get_xl(env)) {
> +    case MXL_RV32:
> +        vill = (uint32_t)env->vill << 31;
> +        break;
> +    case MXL_RV64:
> +        vill = (uint64_t)env->vill << 63;
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +    *val = (target_ulong)vill | env->vtype;
>      return RISCV_EXCP_NONE;
>  }
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 19e982d3f0..ec7584f256 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -94,8 +94,8 @@ static bool pointermasking_needed(void *opaque)
>
>  static const VMStateDescription vmstate_vector = {
>      .name = "cpu/vector",
> -    .version_id = 1,
> -    .minimum_version_id = 1,
> +    .version_id = 2,
> +    .minimum_version_id = 2,
>      .needed = vector_needed,
>      .fields = (VMStateField[]) {
>              VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
> @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = {
>              VMSTATE_UINTTL(env.vl, RISCVCPU),
>              VMSTATE_UINTTL(env.vstart, RISCVCPU),
>              VMSTATE_UINTTL(env.vtype, RISCVCPU),
> +            VMSTATE_BOOL(env.vill, RISCVCPU),
>              VMSTATE_END_OF_LIST()
>          }
>  };
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 12c31aa4b4..b02ccefa4d 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -38,7 +38,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, 
> target_ulong s1,
>
>      if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
>          /* only set vill bit. */
> -        env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> +        env->vill = 1;
> +        env->vtype = 0;
>          env->vl = 0;
>          env->vstart = 0;
>          return 0;
> --
> 2.25.1
>
>