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Re: [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN |
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Date: |
Fri, 19 Nov 2021 22:34:58 +1000 |
On Fri, Nov 12, 2021 at 2:11 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6fa673f4b2..6cc83356d9 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
> (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
> vext_check_reg(s, a->rd, false) &&
> vext_check_reg(s, a->rs2, false) &&
> - ((1 << s->sew) <= sizeof(target_ulong)) &&
> + /* TODO: RV128 could allow 128-bit atomics */
> + ((1 << s->sew) <= (get_xl(s) == MXL_RV32 ? 4 : 8)) &&
> ((1 << s->sew) >= 4));
> }
>
> --
> 2.25.1
>
>
- Re: [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base, (continued)
- [PATCH v4 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/11
- [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN,
Alistair Francis <=
- [PATCH v4 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
- [PATCH v4 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
- [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 00/20] Support UXL filed in xstatus, Alistair Francis, 2021/11/19