Re: [PATCH v4 20/20] target/riscv: Enable uxl field write

qemu-riscv

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Re: [PATCH v4 20/20] target/riscv: Enable uxl field write

From:	Richard Henderson
Subject:	Re: [PATCH v4 20/20] target/riscv: Enable uxl field write
Date:	Thu, 11 Nov 2021 19:23:52 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/11/21 4:51 PM, LIU Zhiwei wrote:

Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
---
  target/riscv/cpu_bits.h | 2 ++
  target/riscv/csr.c      | 8 +++++---
  2 files changed, 7 insertions(+), 3 deletions(-)


Works for me.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, (continued)
- [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/11
  - Re: [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 2021/11/19
- [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/11
  - Re: [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, Alistair Francis, 2021/11/19
- [PATCH v4 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
  - Re: [PATCH v4 17/20] target/riscv: Fix check range for first fault only, Alistair Francis, 2021/11/19
- [PATCH v4 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
  - Re: [PATCH v4 18/20] target/riscv: Adjust vector address with mask, Alistair Francis, 2021/11/19
- [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11
  - Re: [PATCH v4 20/20] target/riscv: Enable uxl field write, Richard Henderson <=
  - Re: [PATCH v4 20/20] target/riscv: Enable uxl field write, Alistair Francis, 2021/11/19
- Re: [PATCH v4 00/20] Support UXL filed in xstatus, Alistair Francis, 2021/11/19
  - Re: [PATCH v4 00/20] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/19

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