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Re: [PATCH v4 17/20] target/riscv: Fix check range for first fault only
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 17/20] target/riscv: Fix check range for first fault only |
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Date: |
Fri, 19 Nov 2021 22:42:15 +1000 |
On Fri, Nov 12, 2021 at 2:05 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Only check the range that has passed the address translation.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index e49b431610..4cd6476b82 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -630,12 +630,12 @@ vext_ldff(void *vd, void *v0, target_ulong base,
> cpu_mmu_index(env, false));
> if (host) {
> #ifdef CONFIG_USER_ONLY
> - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
> + if (page_check_range(addr, offset, PAGE_READ) < 0) {
> vl = i;
> goto ProbeSuccess;
> }
> #else
> - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
> + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
> #endif
> } else {
> vl = i;
> --
> 2.25.1
>
>
- Re: [PATCH v4 12/20] target/riscv: Split out the vill from vtype, (continued)
- [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 17/20] target/riscv: Fix check range for first fault only,
Alistair Francis <=
- [PATCH v4 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
- [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 00/20] Support UXL filed in xstatus, Alistair Francis, 2021/11/19