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Re: Static pattern usage

From: Sam Ravnborg
Subject: Re: Static pattern usage
Date: Fri, 3 Oct 2003 23:05:10 +0200
User-agent: Mutt/1.4.1i

On Fri, Oct 03, 2003 at 11:01:02PM +0200, Sam Ravnborg wrote:
> I'm having troubles using static patters.
> See following example:
> ------------------------------------
> deps_foo.o := foo.h
> foo.o : % : $(deps_%) bar.h FORCE
>         @echo $^
> ------------------------------------
> When executed I expected it to print:
> foo.h bar.h FORCE
> But it only prints bar.h FORCE
> Is it coorect behaviour that make does not expand the variable
> $(deps_foo.o)?
> % is equal to foo.o in the above example, and the varibale is
> constructed correct. But it is not expanded.

Short question..
Is there any other way to get the name of the target
to be used in the prerequisite list?
Other make implementation expands $* to the name of
the target when listed in the prerequisites, but not gnu make.


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