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Re: Static pattern usage

From: Peter A. Kerzum
Subject: Re: Static pattern usage
Date: Mon, 06 Oct 2003 13:53:48 +0400
User-agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.2) Gecko/20030208 Netscape/7.02

I used this trick with rather complex define/eval constructs
It really works but sometimes gives me 'virtual memory exhaused'
If you (Sam) are interested, I can give you precise example.
If only I figured out how to work out this (endless loop?)
my build system would be perfect =)

Paul D. Smith wrote:
%% Sam Ravnborg <address@hidden> writes:

  sr> Is there any other way to get the name of the target
  sr> to be used in the prerequisite list?
  sr> Other make implementation expands $* to the name of
  sr> the target when listed in the prerequisites, but not gnu make.

No make expands $* in the prerequisites list to the name of the target.

Some makes support a feature where $$@ (note two $'s!) in the
prerequisites list will expand to the name of the target.  GNU make also
supports this syntax (see the GNU make manual).

However, this won't help you because again, the $$@ is not expanded
until _after_ all the other variables are expanded.  This is true even
for other versions of make which support this syntax.

The only way to do what you want is to use the $(eval ...) function to
declare extra dependencies.  Something like:

  OBJS = foo.o
  deps_foo.o := foo.h

  $(foreach target,$(OBJS),$(eval $(target): $$(deps_$(target))))

(note, this is untested).

Best Regards,
Peter A. Kerzum

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