Re: [Discuss-gnuradio] USRP packet parsing

[Thibaud Hottelier]

How do the fpga know is data is interleaved or not ?

I am still worried about the number of fifo that will be used and their 
size. The FPGA looks pretty full. Is there a way to have a memory 
separated from the FPGA that I could access through a bus?

Thibaud

Brian Padalino wrote:
> Something else I noticed was with the channel definition stating that
> the IQ data is to be interleaved.  This shouldn't necessarily happen
> and there shouldn't be a problem with having the block rams be in a
> x32 configuration and each location has an IQ pair associated with it.
> This would reduce down any complexity when dealing with
> deinterleaving the data coming out, and add to the readability of the
> code.
>
> Comments?
>
> Brian