Re: [Discuss-gnuradio] USRP packet parsing

[Eric Blossom]

On Wed, Mar 21, 2007 at 12:52:30PM -0400, Brian Padalino wrote:
> On 3/21/07, Thibaud Hottelier <address@hidden> wrote:
> >How do the fpga know is data is interleaved or not ?
> 
> I believe all samples sent down is interleaved over USB to 16-bit I
> followed by 16-bit Q samples.

See below for more about 1, 2, 4, 8 and 16-bit I/Q.

> These can be concatenated (since they are of the same sample time)
> to 1 32-bit number to store within a block ram within the FPGA.

Yes.

> Doing real-only transmissions could possibly be a status bit to say
> what the data format is?

I think that the format should be an attribute of the data channel.
Below is the current format register def.  Assume we (eventually)
support 1, 2, 4, 8 and 16 bit components.  The half-band bit (B)
probably ought to get moved to a different register.

  /*!
   * \brief Specify Rx data format.
   *
   * \param format      format specifier
   *
   * Rx data format control register
   *
   *     3                   2                   1                       
   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
   *  +-----------------------------------------+-+-+---------+-------+
   *  |          Reserved (Must be zero)        |B|Q|  WIDTH  | SHIFT |
   *  +-----------------------------------------+-+-+---------+-------+
   *
   *  SHIFT specifies arithmetic right shift [0, 15]
   *  WIDTH specifies bit-width of I & Q samples across the USB [1, 16] (not 
all valid)
   *  Q     if set deliver both I & Q, else just I
   *  B     if set bypass half-band filter.
   *
   * Right now the acceptable values are:
   *
   *   B  Q  WIDTH  SHIFT
   *   0  1    16     0
   *   0  1     8     8
   *
   * More valid combos to come.
   *
   * Default value is 0x00000300  16-bits, 0 shift, deliver both I & Q.
   */


> >I am still worried about the number of fifo that will be used and their
> >size. The FPGA looks pretty full. Is there a way to have a memory
> >separated from the FPGA that I could access through a bus?
> 
> We'll be removing one of the RX channels I believe, which frees up a
> multiplier and a whole boatload of memory.  Moreover, the Cyclone has
> special hard memory blocks that are 4096 bits of dual-port memory.
> That gives us 128 locations for complex sample storage in a single
> block.  If more blocks are used (which are available), you just double
> the number every time.
> 
> It's a lot of FIFOs, but if they are necessary then you have to use
> them.  It's a trade off that you should be aware of, but is also
> easily checked.  Download Quartus II from altera.com and compile the
> design for the target FPGA.  Disable the other RX channel and
> re-compile to see the change in resources.
> 
> What do you think?

Sounds good to me.

> >Thibaud
> 
> Brian

Eric