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[PULL 00/33] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 00/33] target-arm queue |
Date: |
Tue, 19 Jan 2021 15:10:31 +0000 |
Arm pullreq: Rémi's ARMv8.4-SEL2 support is the big thing here.
thanks
-- PMM
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
Merge remote-tracking branch
'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19
11:57:07 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210119
for you to fetch changes up to 6d39956891b3d1857af84f72f0230a6d99eb3b6a:
docs: Build and install all the docs in a single manual (2021-01-19 14:38:53
+0000)
----------------------------------------------------------------
target-arm queue:
* Implement IMPDEF pauth algorithm
* Support ARMv8.4-SEL2
* Fix bug where we were truncating predicate vector lengths in SVE insns
* Implement new pvpanic-pci device
* npcm7xx_adc-test: Fix memleak in adc_qom_set
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
* docs: Build and install all the docs in a single manual
----------------------------------------------------------------
Gan Qixin (1):
npcm7xx_adc-test: Fix memleak in adc_qom_set
Mihai Carabas (4):
hw/misc/pvpanic: split-out generic and bus dependent code
hw/misc/pvpanic: add PCI interface support
pvpanic : update pvpanic spec document
tests/qtest: add a test case for pvpanic-pci
Peter Maydell (1):
docs: Build and install all the docs in a single manual
Philippe Mathieu-Daudé (1):
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
Richard Henderson (7):
target/arm: Implement an IMPDEF pauth algorithm
target/arm: Add cpu properties to control pauth
target/arm: Use object_property_add_bool for "sve" property
target/arm: Introduce PREDDESC field definitions
target/arm: Update PFIRST, PNEXT for pred_desc
target/arm: Update ZIP, UZP, TRN for pred_desc
target/arm: Update REV, PUNPK for pred_desc
Rémi Denis-Courmont (19):
target/arm: remove redundant tests
target/arm: add arm_is_el2_enabled() helper
target/arm: use arm_is_el2_enabled() where applicable
target/arm: use arm_hcr_el2_eff() where applicable
target/arm: factor MDCR_EL2 common handling
target/arm: Define isar_feature function to test for presence of SEL2
target/arm: add 64-bit S-EL2 to EL exception table
target/arm: add MMU stage 1 for Secure EL2
target/arm: add ARMv8.4-SEL2 system registers
target/arm: handle VMID change in secure state
target/arm: do S1_ptw_translate() before address space lookup
target/arm: translate NS bit in page-walks
target/arm: generalize 2-stage page-walk condition
target/arm: secure stage 2 translation regime
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
target/arm: revector to run-time pick target EL
target/arm: Implement SCR_EL2.EEL2
target/arm: enable Secure EL2 in max CPU
target/arm: refactor vae1_tlbmask()
docs/conf.py | 46 ++++-
docs/devel/conf.py | 15 --
docs/index.html.in | 17 --
docs/interop/conf.py | 28 ---
docs/meson.build | 64 +++---
docs/specs/conf.py | 16 --
docs/specs/pci-ids.txt | 1 +
docs/specs/pvpanic.txt | 13 +-
docs/system/arm/cpu-features.rst | 21 ++
docs/system/conf.py | 28 ---
docs/tools/conf.py | 37 ----
docs/user/conf.py | 15 --
include/hw/misc/pvpanic.h | 24 ++-
include/hw/pci/pci.h | 1 +
include/qemu/xxhash.h | 98 +++++++++
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 107 ++++++++--
target/arm/internals.h | 45 +++++
hw/misc/pvpanic-isa.c | 94 +++++++++
hw/misc/pvpanic-pci.c | 95 +++++++++
hw/misc/pvpanic.c | 85 +-------
target/arm/cpu.c | 23 ++-
target/arm/cpu64.c | 65 ++++--
target/arm/helper-a64.c | 8 +-
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
target/arm/m_helper.c | 2 +-
target/arm/monitor.c | 1 +
target/arm/op_helper.c | 4 +-
target/arm/pauth_helper.c | 27 ++-
target/arm/sve_helper.c | 33 ++--
target/arm/tlb_helper.c | 3 +
target/arm/translate-a64.c | 4 +
target/arm/translate-sve.c | 31 ++-
target/arm/translate.c | 36 +++-
tests/qtest/arm-cpu-features.c | 13 ++
tests/qtest/npcm7xx_adc-test.c | 1 +
tests/qtest/pvpanic-pci-test.c | 62 ++++++
.gitlab-ci.yml | 4 +-
hw/i386/Kconfig | 2 +-
hw/misc/Kconfig | 12 +-
hw/misc/meson.build | 4 +-
tests/qtest/meson.build | 3 +-
42 files changed, 1080 insertions(+), 524 deletions(-)
delete mode 100644 docs/devel/conf.py
delete mode 100644 docs/index.html.in
delete mode 100644 docs/interop/conf.py
delete mode 100644 docs/specs/conf.py
delete mode 100644 docs/system/conf.py
delete mode 100644 docs/tools/conf.py
delete mode 100644 docs/user/conf.py
create mode 100644 hw/misc/pvpanic-isa.c
create mode 100644 hw/misc/pvpanic-pci.c
create mode 100644 tests/qtest/pvpanic-pci-test.c
- [PULL 00/33] target-arm queue,
Peter Maydell <=
- [PULL 01/33] target/arm: Implement an IMPDEF pauth algorithm, Peter Maydell, 2021/01/19
- [PULL 03/33] target/arm: Use object_property_add_bool for "sve" property, Peter Maydell, 2021/01/19
- [PULL 05/33] target/arm: add arm_is_el2_enabled() helper, Peter Maydell, 2021/01/19
- [PULL 02/33] target/arm: Add cpu properties to control pauth, Peter Maydell, 2021/01/19
- [PULL 07/33] target/arm: use arm_hcr_el2_eff() where applicable, Peter Maydell, 2021/01/19
- [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2, Peter Maydell, 2021/01/19
- [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable, Peter Maydell, 2021/01/19
- [PULL 04/33] target/arm: remove redundant tests, Peter Maydell, 2021/01/19
- [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2, Peter Maydell, 2021/01/19
- [PULL 08/33] target/arm: factor MDCR_EL2 common handling, Peter Maydell, 2021/01/19