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[PULL 09/33] target/arm: Define isar_feature function to test for presen
From: |
Peter Maydell |
Subject: |
[PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2 |
Date: |
Tue, 19 Jan 2021 15:10:40 +0000 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-6-remi.denis.courmont@huawei.com
[PMM: tweaked commit message to match reduced scope of patch
following rebase]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 66e36032949..22a3c8a4cfb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4011,6 +4011,11 @@ static inline bool isar_feature_aa64_sve(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
}
+static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
+}
+
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
--
2.20.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2021/01/19
- [PULL 01/33] target/arm: Implement an IMPDEF pauth algorithm, Peter Maydell, 2021/01/19
- [PULL 03/33] target/arm: Use object_property_add_bool for "sve" property, Peter Maydell, 2021/01/19
- [PULL 05/33] target/arm: add arm_is_el2_enabled() helper, Peter Maydell, 2021/01/19
- [PULL 02/33] target/arm: Add cpu properties to control pauth, Peter Maydell, 2021/01/19
- [PULL 07/33] target/arm: use arm_hcr_el2_eff() where applicable, Peter Maydell, 2021/01/19
- [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2,
Peter Maydell <=
- [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable, Peter Maydell, 2021/01/19
- [PULL 04/33] target/arm: remove redundant tests, Peter Maydell, 2021/01/19
- [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2, Peter Maydell, 2021/01/19
- [PULL 08/33] target/arm: factor MDCR_EL2 common handling, Peter Maydell, 2021/01/19
- [PULL 13/33] target/arm: handle VMID change in secure state, Peter Maydell, 2021/01/19
- [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table, Peter Maydell, 2021/01/19
- [PULL 15/33] target/arm: translate NS bit in page-walks, Peter Maydell, 2021/01/19
- [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers, Peter Maydell, 2021/01/19
- [PULL 17/33] target/arm: secure stage 2 translation regime, Peter Maydell, 2021/01/19
- [PULL 21/33] target/arm: enable Secure EL2 in max CPU, Peter Maydell, 2021/01/19