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[PULL 04/33] target/arm: remove redundant tests
From: |
Peter Maydell |
Subject: |
[PULL 04/33] target/arm: remove redundant tests |
Date: |
Tue, 19 Jan 2021 15:10:35 +0000 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
In this context, the HCR value is the effective value, and thus is
zero in secure mode. The tests for HCR.{F,I}MO are sufficient.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-1-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 8 ++++----
target/arm/helper.c | 10 ++++------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be18df5464d..4ae22b2086b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -451,14 +451,14 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
break;
case EXCP_VFIQ:
- if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
- /* VFIQs are only taken when hypervized and non-secure. */
+ if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
+ /* VFIQs are only taken when hypervized. */
return false;
}
return !(env->daif & PSTATE_F);
case EXCP_VIRQ:
- if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
- /* VIRQs are only taken when hypervized and non-secure. */
+ if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
+ /* VIRQs are only taken when hypervized. */
return false;
}
return !(env->daif & PSTATE_I);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c5377e7ecb3..b2ea93c4722 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2084,13 +2084,11 @@ static void csselr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
CPUState *cs = env_cpu(env);
- uint64_t hcr_el2 = arm_hcr_el2_eff(env);
+ bool el1 = arm_current_el(env) == 1;
+ uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0;
uint64_t ret = 0;
- bool allow_virt = (arm_current_el(env) == 1 &&
- (!arm_is_secure_below_el3(env) ||
- (env->cp15.scr_el3 & SCR_EEL2)));
- if (allow_virt && (hcr_el2 & HCR_IMO)) {
+ if (hcr_el2 & HCR_IMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
ret |= CPSR_I;
}
@@ -2100,7 +2098,7 @@ static uint64_t isr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
}
- if (allow_virt && (hcr_el2 & HCR_FMO)) {
+ if (hcr_el2 & HCR_FMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
ret |= CPSR_F;
}
--
2.20.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2021/01/19
- [PULL 01/33] target/arm: Implement an IMPDEF pauth algorithm, Peter Maydell, 2021/01/19
- [PULL 03/33] target/arm: Use object_property_add_bool for "sve" property, Peter Maydell, 2021/01/19
- [PULL 05/33] target/arm: add arm_is_el2_enabled() helper, Peter Maydell, 2021/01/19
- [PULL 02/33] target/arm: Add cpu properties to control pauth, Peter Maydell, 2021/01/19
- [PULL 07/33] target/arm: use arm_hcr_el2_eff() where applicable, Peter Maydell, 2021/01/19
- [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2, Peter Maydell, 2021/01/19
- [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable, Peter Maydell, 2021/01/19
- [PULL 04/33] target/arm: remove redundant tests,
Peter Maydell <=
- [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2, Peter Maydell, 2021/01/19
- [PULL 08/33] target/arm: factor MDCR_EL2 common handling, Peter Maydell, 2021/01/19
- [PULL 13/33] target/arm: handle VMID change in secure state, Peter Maydell, 2021/01/19
- [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table, Peter Maydell, 2021/01/19
- [PULL 15/33] target/arm: translate NS bit in page-walks, Peter Maydell, 2021/01/19
- [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers, Peter Maydell, 2021/01/19
- [PULL 17/33] target/arm: secure stage 2 translation regime, Peter Maydell, 2021/01/19
- [PULL 21/33] target/arm: enable Secure EL2 in max CPU, Peter Maydell, 2021/01/19
- [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup, Peter Maydell, 2021/01/19
- [PULL 16/33] target/arm: generalize 2-stage page-walk condition, Peter Maydell, 2021/01/19