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[PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is di
From: |
Peter Maydell |
Subject: |
[PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled |
Date: |
Tue, 2 Feb 2021 17:55:07 +0000 |
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_soft_reset() is called to reset the controller, but chip
select lines should have been disabled, otherwise the state machine
of any devices (e.g.: SPI flashes) connected to the SPI master is
stuck to its last state and responds incorrectly to any follow-up
commands.
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ssi/imx_spi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 4cfbb73e35e..2fb65498c3b 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s)
static void imx_spi_soft_reset(IMXSPIState *s)
{
+ int i;
+
imx_spi_common_reset(s);
imx_spi_update_irq(s);
+
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
+ qemu_set_irq(s->cs_lines[i], 1);
+ }
}
static void imx_spi_reset(DeviceState *dev)
--
2.20.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2021/02/02
- [PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input, Peter Maydell, 2021/02/02
- [PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled, Peter Maydell, 2021/02/02
- [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported, Peter Maydell, 2021/02/02
- [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled,
Peter Maydell <=
- [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Peter Maydell, 2021/02/02
- [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization, Peter Maydell, 2021/02/02
- [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing, Peter Maydell, 2021/02/02
- [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation, Peter Maydell, 2021/02/02
- [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled, Peter Maydell, 2021/02/02
- [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Peter Maydell, 2021/02/02
- [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register, Peter Maydell, 2021/02/02
- [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Peter Maydell, 2021/02/02
- [PULL 17/21] hw/arm/exynos4210: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02