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[PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple o
From: |
Peter Maydell |
Subject: |
[PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 |
Date: |
Tue, 2 Feb 2021 17:55:08 +0000 |
From: Bin Meng <bin.meng@windriver.com>
Current implementation of the imx spi controller expects the burst
length to be multiple of 8, which is the most common use case.
In case the burst length is not what we expect, log it to give user
a chance to notice it, and round it up to be multiple of 8.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20210129132323.30946-9-bmeng.cn@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ssi/imx_spi.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 2fb65498c3b..41fe199c9f1 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -128,7 +128,14 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s)
static uint32_t imx_spi_burst_length(IMXSPIState *s)
{
- return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ uint32_t burst;
+
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ if (burst % 8) {
+ burst = ROUND_UP(burst, 8);
+ }
+
+ return burst;
}
static bool imx_spi_is_enabled(IMXSPIState *s)
@@ -328,6 +335,7 @@ static void imx_spi_write(void *opaque, hwaddr offset,
uint64_t value,
IMXSPIState *s = opaque;
uint32_t index = offset >> 2;
uint32_t change_mask;
+ uint32_t burst;
if (index >= ECSPI_MAX) {
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
@@ -380,6 +388,13 @@ static void imx_spi_write(void *opaque, hwaddr offset,
uint64_t value,
case ECSPI_CONREG:
s->regs[ECSPI_CONREG] = value;
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ if (burst % 8) {
+ qemu_log_mask(LOG_UNIMP,
+ "[%s]%s: burst length %d not supported: rounding up
to next multiple of 8\n",
+ TYPE_IMX_SPI, __func__, burst);
+ }
+
if (!imx_spi_is_enabled(s)) {
/* device is disabled, so this is a soft reset */
imx_spi_soft_reset(s);
--
2.20.1
- [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported, (continued)
- [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported, Peter Maydell, 2021/02/02
- [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled, Peter Maydell, 2021/02/02
- [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Peter Maydell, 2021/02/02
- [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization, Peter Maydell, 2021/02/02
- [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing, Peter Maydell, 2021/02/02
- [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation, Peter Maydell, 2021/02/02
- [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled, Peter Maydell, 2021/02/02
- [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Peter Maydell, 2021/02/02
- [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register, Peter Maydell, 2021/02/02
- [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8,
Peter Maydell <=
- [PULL 17/21] hw/arm/exynos4210: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA, Peter Maydell, 2021/02/02
- [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER, Peter Maydell, 2021/02/02
- [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset(), Peter Maydell, 2021/02/02
- [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled, Peter Maydell, 2021/02/02
- [PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness, Peter Maydell, 2021/02/02
- [PULL 21/21] hw/arm: Display CPU type in machine description, Peter Maydell, 2021/02/02
- [PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals, Peter Maydell, 2021/02/02
- Re: [PULL 00/21] target-arm queue, Philippe Mathieu-Daudé, 2021/02/03