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[PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation
From: |
Peter Maydell |
Subject: |
[PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation |
Date: |
Tue, 2 Feb 2021 17:55:00 +0000 |
From: Zenghui Yu <yuzenghui@huawei.com>
When handling guest range-based IOTLB invalidation, we should decode the TG
field into the corresponding translation granule size so that we can pass
the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to
properly emulate the architecture.
Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210130043220.1345-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index bbca0e9f209..98b99d4fe8e 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
{
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
IOMMUTLBEvent event;
- uint8_t granule = tg;
+ uint8_t granule;
if (!tg) {
SMMUEventInfo event = {.inval_ste_allowed = true};
@@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
return;
}
granule = tt->granule_sz;
+ } else {
+ granule = tg * 2 + 10;
}
event.type = IOMMU_NOTIFIER_UNMAP;
--
2.20.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2021/02/02
- [PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input, Peter Maydell, 2021/02/02
- [PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled, Peter Maydell, 2021/02/02
- [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported, Peter Maydell, 2021/02/02
- [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled, Peter Maydell, 2021/02/02
- [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Peter Maydell, 2021/02/02
- [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization, Peter Maydell, 2021/02/02
- [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing, Peter Maydell, 2021/02/02
- [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation,
Peter Maydell <=
- [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled, Peter Maydell, 2021/02/02
- [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Peter Maydell, 2021/02/02
- [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register, Peter Maydell, 2021/02/02
- [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Peter Maydell, 2021/02/02
- [PULL 17/21] hw/arm/exynos4210: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA, Peter Maydell, 2021/02/02
- [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER, Peter Maydell, 2021/02/02
- [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset(), Peter Maydell, 2021/02/02
- [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled, Peter Maydell, 2021/02/02