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[PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_res
From: |
Peter Maydell |
Subject: |
[PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() |
Date: |
Tue, 2 Feb 2021 17:55:02 +0000 |
From: Bin Meng <bin.meng@windriver.com>
Usually the approach is that the device on the other end of the line
is going to reset its state anyway, so there's no need to actively
signal an irq line change during the reset hook.
Move imx_spi_update_irq() out of imx_spi_reset(), to a new function
imx_spi_soft_reset() that is called when the controller is disabled.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210129132323.30946-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ssi/imx_spi.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index e605049a213..4d488b159af 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev)
imx_spi_rxfifo_reset(s);
imx_spi_txfifo_reset(s);
- imx_spi_update_irq(s);
-
s->burst_length = 0;
}
+static void imx_spi_soft_reset(IMXSPIState *s)
+{
+ imx_spi_reset(DEVICE(s));
+
+ imx_spi_update_irq(s);
+}
+
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t value = 0;
@@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset,
uint64_t value,
s->regs[ECSPI_CONREG] = value;
if (!imx_spi_is_enabled(s)) {
- /* device is disabled, so this is a reset */
- imx_spi_reset(DEVICE(s));
+ /* device is disabled, so this is a soft reset */
+ imx_spi_soft_reset(s);
+
return;
}
--
2.20.1
- [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing, (continued)
- [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing, Peter Maydell, 2021/02/02
- [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation, Peter Maydell, 2021/02/02
- [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled, Peter Maydell, 2021/02/02
- [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Peter Maydell, 2021/02/02
- [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register, Peter Maydell, 2021/02/02
- [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Peter Maydell, 2021/02/02
- [PULL 17/21] hw/arm/exynos4210: Add missing dependency on OR_IRQ, Peter Maydell, 2021/02/02
- [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA, Peter Maydell, 2021/02/02
- [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER, Peter Maydell, 2021/02/02
- [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset(),
Peter Maydell <=
- [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled, Peter Maydell, 2021/02/02
- [PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness, Peter Maydell, 2021/02/02
- [PULL 21/21] hw/arm: Display CPU type in machine description, Peter Maydell, 2021/02/02
- [PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals, Peter Maydell, 2021/02/02
- Re: [PULL 00/21] target-arm queue, Philippe Mathieu-Daudé, 2021/02/03