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Re: [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware re
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware reset |
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Date: |
Thu, 2 Sep 2021 20:31:14 +0100 |
On Thu, 2 Sept 2021 at 18:46, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> On 02/09/2021 16:42, Peter Maydell wrote:
>
> > On Thu, 2 Sept 2021 at 11:33, Mark Cave-Ayland
> > <mark.cave-ayland@ilande.co.uk> wrote:
> >>
> >> This new hardware reset function is to be called for both channels when the
> >> hardware reset bit is written to register WR9. Its initial implementation
> >> is
> >> the same as the existing escc_reset_chn() function used for device reset.
> >>
> >> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> >
> >
> > The datasheet says the only differences between hard and soft
> > reset are for registers W9, W10, W11 and W14. I wasn't expecting
> > the functions to be completely separated out like this.
>
> I did consider doing it that way, but felt having the 2 separate functions
> was the
> easiest to read against the tables in the datasheet. What do you think would
> be the
> best way to organise the reset functions?
I think having the hard-reset be "call the soft-reset and then
clear/set the handful of bits that hard-reset touches and
soft-reset doesn't" is probably clearer overall.
-- PMM
[PATCH v2 5/9] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/02
[PATCH v2 6/9] escc: implement hard reset as described in the datasheet, Mark Cave-Ayland, 2021/09/02
[PATCH v2 7/9] escc: remove register changes from escc_reset_chn(), Mark Cave-Ayland, 2021/09/02
[PATCH v2 8/9] escc: re-use escc_reset_chn() for hard and soft reset, Mark Cave-Ayland, 2021/09/02
[PATCH v2 9/9] escc: fix STATUS_SYNC bit in R_STATUS register, Mark Cave-Ayland, 2021/09/02