[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the
From: |
Peter Maydell |
Subject: |
[PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase |
Date: |
Mon, 13 Sep 2021 17:11:22 +0100 |
From: Bin Meng <bmeng.cn@gmail.com>
As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
does not receive anything. Debugging shows that the UART input clock
frequency is zero which prevents the UART from receiving anything as
per the logic in uart_receive().
>From zynq_slcr_reset_exit() comment, it intends to compute output
clocks according to ps_clk and registers. zynq_slcr_compute_clocks()
is called to accomplish the task, inside which device_is_in_reset()
is called to actually make the attempt in vain.
Rework reset_hold() and reset_exit() so that in the reset exit phase,
the logic can really compute output clocks in reset_exit().
With this change, upstream U-Boot boots properly again with:
$ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial
stdio \
-device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0
Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210901124521.30599-2-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/zynq_slcr.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 5086e6b7ed2..8b702859618 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -269,6 +269,21 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t
periods[],
zynq_slcr_compute_clock((plls), (state)->regs[reg], \
reg ## _ ## enable_field ## _SHIFT)
+static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t
ps_clk)
+{
+ uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
+ uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
+ uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
+
+ uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
+
+ /* compute uartX reference clocks */
+ clock_set(s->uart0_ref_clk,
+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
+ clock_set(s->uart1_ref_clk,
+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
+}
+
/**
* Compute and set the ouputs clocks periods.
* But do not propagate them further. Connected clocks
@@ -283,17 +298,7 @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
ps_clk = 0;
}
- uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
- uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
- uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
-
- uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
-
- /* compute uartX reference clocks */
- clock_set(s->uart0_ref_clk,
- ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
- clock_set(s->uart1_ref_clk,
- ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
+ zynq_slcr_compute_clocks_internal(s, ps_clk);
}
/**
@@ -416,7 +421,7 @@ static void zynq_slcr_reset_hold(Object *obj)
ZynqSLCRState *s = ZYNQ_SLCR(obj);
/* will disable all output clocks */
- zynq_slcr_compute_clocks(s);
+ zynq_slcr_compute_clocks_internal(s, 0);
zynq_slcr_propagate_clocks(s);
}
@@ -425,7 +430,7 @@ static void zynq_slcr_reset_exit(Object *obj)
ZynqSLCRState *s = ZYNQ_SLCR(obj);
/* will compute output clocks according to ps_clk and registers */
- zynq_slcr_compute_clocks(s);
+ zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk));
zynq_slcr_propagate_clocks(s);
}
--
2.20.1
- [PULL 00/23] target-arm queue, Peter Maydell, 2021/09/13
- [PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase,
Peter Maydell <=
- [PULL 02/23] hw/char: cadence_uart: Disable transmit when input clock is disabled, Peter Maydell, 2021/09/13
- [PULL 03/23] hw/char: cadence_uart: Move clock/reset check to uart_can_receive(), Peter Maydell, 2021/09/13
- [PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops, Peter Maydell, 2021/09/13
- [PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}(), Peter Maydell, 2021/09/13
- [PULL 06/23] hw/char: cadence_uart: Log a guest error when device is unclocked or in reset, Peter Maydell, 2021/09/13
- [PULL 07/23] hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM, Peter Maydell, 2021/09/13
- [PULL 08/23] hw/arm: Add support for kudo-bmc board., Peter Maydell, 2021/09/13
- [PULL 09/23] hw/intc: GICv3 ITS initial framework, Peter Maydell, 2021/09/13
- [PULL 11/23] hw/intc: GICv3 ITS command queue framework, Peter Maydell, 2021/09/13
- [PULL 10/23] hw/intc: GICv3 ITS register definitions added, Peter Maydell, 2021/09/13