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[PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops
From: |
Peter Maydell |
Subject: |
[PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops |
Date: |
Mon, 13 Sep 2021 17:11:25 +0100 |
From: Bin Meng <bmeng.cn@gmail.com>
This converts uart_read() and uart_write() to memop_with_attrs() ops.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-5-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/cadence_uart.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index fff8be36191..8bcf2b718a0 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -411,15 +411,15 @@ static void uart_read_rx_fifo(CadenceUARTState *s,
uint32_t *c)
uart_update_status(s);
}
-static void uart_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
+static MemTxResult uart_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size, MemTxAttrs attrs)
{
CadenceUARTState *s = opaque;
DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
- return;
+ return MEMTX_DECODE_ERROR;
}
switch (offset) {
case R_IER: /* ier (wts imr) */
@@ -466,30 +466,34 @@ static void uart_write(void *opaque, hwaddr offset,
break;
}
uart_update_status(s);
+
+ return MEMTX_OK;
}
-static uint64_t uart_read(void *opaque, hwaddr offset,
- unsigned size)
+static MemTxResult uart_read(void *opaque, hwaddr offset,
+ uint64_t *value, unsigned size, MemTxAttrs attrs)
{
CadenceUARTState *s = opaque;
uint32_t c = 0;
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
- c = 0;
- } else if (offset == R_TX_RX) {
+ return MEMTX_DECODE_ERROR;
+ }
+ if (offset == R_TX_RX) {
uart_read_rx_fifo(s, &c);
} else {
- c = s->r[offset];
+ c = s->r[offset];
}
DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
- return c;
+ *value = c;
+ return MEMTX_OK;
}
static const MemoryRegionOps uart_ops = {
- .read = uart_read,
- .write = uart_write,
+ .read_with_attrs = uart_read,
+ .write_with_attrs = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
--
2.20.1
- [PULL 00/23] target-arm queue, Peter Maydell, 2021/09/13
- [PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase, Peter Maydell, 2021/09/13
- [PULL 02/23] hw/char: cadence_uart: Disable transmit when input clock is disabled, Peter Maydell, 2021/09/13
- [PULL 03/23] hw/char: cadence_uart: Move clock/reset check to uart_can_receive(), Peter Maydell, 2021/09/13
- [PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops,
Peter Maydell <=
- [PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}(), Peter Maydell, 2021/09/13
- [PULL 06/23] hw/char: cadence_uart: Log a guest error when device is unclocked or in reset, Peter Maydell, 2021/09/13
- [PULL 07/23] hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM, Peter Maydell, 2021/09/13
- [PULL 08/23] hw/arm: Add support for kudo-bmc board., Peter Maydell, 2021/09/13
- [PULL 09/23] hw/intc: GICv3 ITS initial framework, Peter Maydell, 2021/09/13
- [PULL 11/23] hw/intc: GICv3 ITS command queue framework, Peter Maydell, 2021/09/13
- [PULL 10/23] hw/intc: GICv3 ITS register definitions added, Peter Maydell, 2021/09/13
- [PULL 15/23] tests/data/acpi/virt: Add IORT files for ITS, Peter Maydell, 2021/09/13
- [PULL 13/23] hw/intc: GICv3 ITS Feature enablement, Peter Maydell, 2021/09/13
- [PULL 14/23] hw/intc: GICv3 redistributor ITS processing, Peter Maydell, 2021/09/13