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[PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in r
From: |
Peter Maydell |
Subject: |
[PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() |
Date: |
Mon, 13 Sep 2021 17:11:26 +0100 |
From: Bin Meng <bmeng.cn@gmail.com>
Read or write to uart registers when unclocked or in reset should be
ignored. Add the check there, and as a result of this, the check in
uart_write_tx_fifo() is now unnecessary.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-6-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/cadence_uart.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 8bcf2b718a0..5f5a4645ac0 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -335,11 +335,6 @@ static gboolean cadence_uart_xmit(void *do_not_use,
GIOCondition cond,
static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
int size)
{
- /* ignore characters when unclocked or in reset */
- if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
- return;
- }
-
if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
return;
}
@@ -416,6 +411,11 @@ static MemTxResult uart_write(void *opaque, hwaddr offset,
{
CadenceUARTState *s = opaque;
+ /* ignore access when unclocked or in reset */
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+ return MEMTX_ERROR;
+ }
+
DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
@@ -476,6 +476,11 @@ static MemTxResult uart_read(void *opaque, hwaddr offset,
CadenceUARTState *s = opaque;
uint32_t c = 0;
+ /* ignore access when unclocked or in reset */
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+ return MEMTX_ERROR;
+ }
+
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
return MEMTX_DECODE_ERROR;
--
2.20.1
- [PULL 00/23] target-arm queue, Peter Maydell, 2021/09/13
- [PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase, Peter Maydell, 2021/09/13
- [PULL 02/23] hw/char: cadence_uart: Disable transmit when input clock is disabled, Peter Maydell, 2021/09/13
- [PULL 03/23] hw/char: cadence_uart: Move clock/reset check to uart_can_receive(), Peter Maydell, 2021/09/13
- [PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops, Peter Maydell, 2021/09/13
- [PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}(),
Peter Maydell <=
- [PULL 06/23] hw/char: cadence_uart: Log a guest error when device is unclocked or in reset, Peter Maydell, 2021/09/13
- [PULL 07/23] hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM, Peter Maydell, 2021/09/13
- [PULL 08/23] hw/arm: Add support for kudo-bmc board., Peter Maydell, 2021/09/13
- [PULL 09/23] hw/intc: GICv3 ITS initial framework, Peter Maydell, 2021/09/13
- [PULL 11/23] hw/intc: GICv3 ITS command queue framework, Peter Maydell, 2021/09/13
- [PULL 10/23] hw/intc: GICv3 ITS register definitions added, Peter Maydell, 2021/09/13
- [PULL 15/23] tests/data/acpi/virt: Add IORT files for ITS, Peter Maydell, 2021/09/13
- [PULL 13/23] hw/intc: GICv3 ITS Feature enablement, Peter Maydell, 2021/09/13
- [PULL 14/23] hw/intc: GICv3 redistributor ITS processing, Peter Maydell, 2021/09/13
- [PULL 18/23] target/arm: Take an exception if PSTATE.IL is set, Peter Maydell, 2021/09/13