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[PULL 01/23] WHPX: fixed TPR/CR8 translation issues affecting VM debuggi
From: |
Paolo Bonzini |
Subject: |
[PULL 01/23] WHPX: fixed TPR/CR8 translation issues affecting VM debugging |
Date: |
Mon, 16 May 2022 17:55:41 +0200 |
From: Ivan Shcherbakov <ivan@sysprogs.com>
This patch fixes the following error that would occur when trying to resume
a WHPX-accelerated VM from a breakpoint:
qemu: WHPX: Failed to set interrupt state registers, hr=c0350005
The error arises from an incorrect CR8 value being passed to
WHvSetVirtualProcessorRegisters() that doesn't match the
value set via WHvSetVirtualProcessorInterruptControllerState2().
Signed-off-by: Ivan Shcherbakov <ivan@sysprogs.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/whpx/whpx-all.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 23ae639b23..b22a3314b4 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -373,6 +373,8 @@ static int whpx_set_tsc(CPUState *cpu)
*
* This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64
* and IA-32 Architectures Software Developer's Manual.
+ *
+ * The functions below translate the value of CR8 to TPR and vice versa.
*/
static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)
@@ -380,6 +382,11 @@ static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)
return tpr >> 4;
}
+static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)
+{
+ return cr8 << 4;
+}
+
static void whpx_set_registers(CPUState *cpu, int level)
{
struct whpx_state *whpx = &whpx_global;
@@ -687,7 +694,7 @@ static void whpx_get_registers(CPUState *cpu)
tpr = vcxt.values[idx++].Reg64;
if (tpr != vcpu->tpr) {
vcpu->tpr = tpr;
- cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
+ cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));
}
/* 8 Debug Registers - Skipped */
@@ -1547,7 +1554,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
}
/* Sync the TPR to the CR8 if was modified during the intercept */
- tpr = cpu_get_apic_tpr(x86_cpu->apic_state);
+ tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));
if (tpr != vcpu->tpr) {
vcpu->tpr = tpr;
reg_values[reg_count].Reg64 = tpr;
@@ -1596,7 +1603,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)
if (vcpu->tpr != tpr) {
vcpu->tpr = tpr;
qemu_mutex_lock_iothread();
- cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);
+ cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));
qemu_mutex_unlock_iothread();
}
--
2.36.0
- [PULL 00/23] Misc QEMU patches for 2022-05-16, Paolo Bonzini, 2022/05/16
- [PULL 01/23] WHPX: fixed TPR/CR8 translation issues affecting VM debugging,
Paolo Bonzini <=
- [PULL 02/23] qga-vss: Add auto generated headers to dependencies, Paolo Bonzini, 2022/05/16
- [PULL 03/23] qga-vss: Use the proper operator to free memory, Paolo Bonzini, 2022/05/16
- [PULL 05/23] qdev-properties: Add a new macro with bitmask check for uint64_t property, Paolo Bonzini, 2022/05/16
- [PULL 04/23] i386/cpu: Remove the deprecated cpu model 'Icelake-Client', Paolo Bonzini, 2022/05/16
- [PULL 06/23] target/i386: Add lbr-fmt vPMU option to support guest LBR, Paolo Bonzini, 2022/05/16
- [PULL 07/23] target/i386: Add kvm_get_one_msr helper, Paolo Bonzini, 2022/05/16
- [PULL 09/23] target/i386: Add XSAVES support for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 08/23] target/i386: Enable support for XSAVES based features, Paolo Bonzini, 2022/05/16
- [PULL 10/23] target/i386: Add MSR access interface for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 11/23] target/i386: Enable Arch LBR migration states in vmstate, Paolo Bonzini, 2022/05/16