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[PULL 07/23] target/i386: Add kvm_get_one_msr helper
From: |
Paolo Bonzini |
Subject: |
[PULL 07/23] target/i386: Add kvm_get_one_msr helper |
Date: |
Mon, 16 May 2022 17:55:47 +0200 |
From: Yang Weijiang <weijiang.yang@intel.com>
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-4-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/kvm/kvm.c | 46 ++++++++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index c885763a5b..536cbe5fad 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -141,6 +141,7 @@ static struct kvm_msr_list *kvm_feature_msrs;
#define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
static RateLimit bus_lock_ratelimit_ctrl;
+static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
int kvm_has_pit_state2(void)
{
@@ -211,28 +212,21 @@ static int kvm_get_tsc(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- struct {
- struct kvm_msrs info;
- struct kvm_msr_entry entries[1];
- } msr_data = {};
+ uint64_t value;
int ret;
if (env->tsc_valid) {
return 0;
}
- memset(&msr_data, 0, sizeof(msr_data));
- msr_data.info.nmsrs = 1;
- msr_data.entries[0].index = MSR_IA32_TSC;
env->tsc_valid = !runstate_is_running();
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
+ ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
if (ret < 0) {
return ret;
}
- assert(ret == 1);
- env->tsc = msr_data.entries[0].data;
+ env->tsc = value;
return 0;
}
@@ -1566,21 +1560,14 @@ static int hyperv_init_vcpu(X86CPU *cpu)
* the kernel doesn't support setting vp_index; assert that its value
* is in sync
*/
- struct {
- struct kvm_msrs info;
- struct kvm_msr_entry entries[1];
- } msr_data = {
- .info.nmsrs = 1,
- .entries[0].index = HV_X64_MSR_VP_INDEX,
- };
+ uint64_t value;
- ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
+ ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
if (ret < 0) {
return ret;
}
- assert(ret == 1);
- if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
+ if (value != hyperv_vp_index(CPU(cpu))) {
error_report("kernel's vp_index != QEMU's vp_index");
return -ENXIO;
}
@@ -2839,6 +2826,25 @@ static int kvm_put_one_msr(X86CPU *cpu, int index,
uint64_t value)
return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
}
+static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
+{
+ int ret;
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[1];
+ } msr_data = {
+ .info.nmsrs = 1,
+ .entries[0].index = index,
+ };
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
+ if (ret < 0) {
+ return ret;
+ }
+ assert(ret == 1);
+ *value = msr_data.entries[0].data;
+ return ret;
+}
void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
{
int ret;
--
2.36.0
- [PULL 00/23] Misc QEMU patches for 2022-05-16, Paolo Bonzini, 2022/05/16
- [PULL 01/23] WHPX: fixed TPR/CR8 translation issues affecting VM debugging, Paolo Bonzini, 2022/05/16
- [PULL 02/23] qga-vss: Add auto generated headers to dependencies, Paolo Bonzini, 2022/05/16
- [PULL 03/23] qga-vss: Use the proper operator to free memory, Paolo Bonzini, 2022/05/16
- [PULL 05/23] qdev-properties: Add a new macro with bitmask check for uint64_t property, Paolo Bonzini, 2022/05/16
- [PULL 04/23] i386/cpu: Remove the deprecated cpu model 'Icelake-Client', Paolo Bonzini, 2022/05/16
- [PULL 06/23] target/i386: Add lbr-fmt vPMU option to support guest LBR, Paolo Bonzini, 2022/05/16
- [PULL 07/23] target/i386: Add kvm_get_one_msr helper,
Paolo Bonzini <=
- [PULL 09/23] target/i386: Add XSAVES support for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 08/23] target/i386: Enable support for XSAVES based features, Paolo Bonzini, 2022/05/16
- [PULL 10/23] target/i386: Add MSR access interface for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 11/23] target/i386: Enable Arch LBR migration states in vmstate, Paolo Bonzini, 2022/05/16
- [PULL 12/23] target/i386: introduce helper to access supported CPUID, Paolo Bonzini, 2022/05/16
- [PULL 13/23] target/i386: Support Arch LBR in CPUID enumeration, Paolo Bonzini, 2022/05/16
- [PULL 15/23] rng: make opened property read-only, Paolo Bonzini, 2022/05/16
- [PULL 16/23] soundhw: remove ability to create multiple soundcards, Paolo Bonzini, 2022/05/16
- [PULL 17/23] soundhw: extract soundhw help to a separate function, Paolo Bonzini, 2022/05/16
- [PULL 18/23] soundhw: unify initialization for ISA and PCI soundhw, Paolo Bonzini, 2022/05/16