[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 09/23] target/i386: Add XSAVES support for Arch LBR
From: |
Paolo Bonzini |
Subject: |
[PULL 09/23] target/i386: Add XSAVES support for Arch LBR |
Date: |
Mon, 16 May 2022 17:55:49 +0200 |
From: Yang Weijiang <weijiang.yang@intel.com>
Define Arch LBR bit in XSS and save/restore structure
for XSAVE area size calculation.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-6-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 6 +++++-
target/i386/cpu.h | 23 +++++++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 643536d05d..1816c37852 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1411,7 +1411,7 @@ static const X86RegisterInfo32
x86_reg_info_32[CPU_NB_REGS32] = {
#undef REGISTER
/* CPUID feature bits available in XSS */
-#define CPUID_XSTATE_XSS_MASK (0)
+#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
[XSTATE_FP_BIT] = {
@@ -1445,6 +1445,10 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] =
{
[XSTATE_PKRU_BIT] =
{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
.size = sizeof(XSavePKRU) },
+ [XSTATE_ARCH_LBR_BIT] = {
+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR,
+ .offset = 0 /*supervisor mode component, offset = 0 */,
+ .size = sizeof(XSavesArchLBR) },
[XSTATE_XTILE_CFG_BIT] = {
.feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
.size = sizeof(XSaveXTILECFG),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 453b80eae2..dba92936a2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -544,6 +544,7 @@ typedef enum X86Seg {
#define XSTATE_ZMM_Hi256_BIT 6
#define XSTATE_Hi16_ZMM_BIT 7
#define XSTATE_PKRU_BIT 9
+#define XSTATE_ARCH_LBR_BIT 15
#define XSTATE_XTILE_CFG_BIT 17
#define XSTATE_XTILE_DATA_BIT 18
@@ -556,6 +557,7 @@ typedef enum X86Seg {
#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
+#define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
@@ -870,6 +872,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
/* TSX Suspend Load Address Tracking instruction */
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
+/* Architectural LBRs */
+#define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
/* AVX512_FP16 instruction */
#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
/* AMX tile (two-dimensional register) */
@@ -1376,6 +1380,24 @@ typedef struct XSaveXTILEDATA {
uint8_t xtiledata[8][1024];
} XSaveXTILEDATA;
+typedef struct {
+ uint64_t from;
+ uint64_t to;
+ uint64_t info;
+} LBREntry;
+
+#define ARCH_LBR_NR_ENTRIES 32
+
+/* Ext. save area 19: Supervisor mode Arch LBR state */
+typedef struct XSavesArchLBR {
+ uint64_t lbr_ctl;
+ uint64_t lbr_depth;
+ uint64_t ler_from;
+ uint64_t ler_to;
+ uint64_t ler_info;
+ LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
+} XSavesArchLBR;
+
QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
@@ -1385,6 +1407,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
+QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
typedef struct ExtSaveArea {
uint32_t feature, bits;
--
2.36.0
- [PULL 00/23] Misc QEMU patches for 2022-05-16, Paolo Bonzini, 2022/05/16
- [PULL 01/23] WHPX: fixed TPR/CR8 translation issues affecting VM debugging, Paolo Bonzini, 2022/05/16
- [PULL 02/23] qga-vss: Add auto generated headers to dependencies, Paolo Bonzini, 2022/05/16
- [PULL 03/23] qga-vss: Use the proper operator to free memory, Paolo Bonzini, 2022/05/16
- [PULL 05/23] qdev-properties: Add a new macro with bitmask check for uint64_t property, Paolo Bonzini, 2022/05/16
- [PULL 04/23] i386/cpu: Remove the deprecated cpu model 'Icelake-Client', Paolo Bonzini, 2022/05/16
- [PULL 06/23] target/i386: Add lbr-fmt vPMU option to support guest LBR, Paolo Bonzini, 2022/05/16
- [PULL 07/23] target/i386: Add kvm_get_one_msr helper, Paolo Bonzini, 2022/05/16
- [PULL 09/23] target/i386: Add XSAVES support for Arch LBR,
Paolo Bonzini <=
- [PULL 08/23] target/i386: Enable support for XSAVES based features, Paolo Bonzini, 2022/05/16
- [PULL 10/23] target/i386: Add MSR access interface for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 11/23] target/i386: Enable Arch LBR migration states in vmstate, Paolo Bonzini, 2022/05/16
- [PULL 12/23] target/i386: introduce helper to access supported CPUID, Paolo Bonzini, 2022/05/16
- [PULL 13/23] target/i386: Support Arch LBR in CPUID enumeration, Paolo Bonzini, 2022/05/16
- [PULL 15/23] rng: make opened property read-only, Paolo Bonzini, 2022/05/16
- [PULL 16/23] soundhw: remove ability to create multiple soundcards, Paolo Bonzini, 2022/05/16
- [PULL 17/23] soundhw: extract soundhw help to a separate function, Paolo Bonzini, 2022/05/16
- [PULL 18/23] soundhw: unify initialization for ISA and PCI soundhw, Paolo Bonzini, 2022/05/16
- [PULL 23/23] configure: remove duplicate help messages, Paolo Bonzini, 2022/05/16