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[PULL 06/23] target/i386: Add lbr-fmt vPMU option to support guest LBR
From: |
Paolo Bonzini |
Subject: |
[PULL 06/23] target/i386: Add lbr-fmt vPMU option to support guest LBR |
Date: |
Mon, 16 May 2022 17:55:46 +0200 |
From: Yang Weijiang <weijiang.yang@intel.com>
The Last Branch Recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors which records a running trace of the most
recent branches taken by the processor in the LBR stack. This option
indicates the LBR format to enable for guest perf.
The LBR feature is enabled if below conditions are met:
1) KVM is enabled and the PMU is enabled.
2) msr-based-feature IA32_PERF_CAPABILITIES is supporterd on KVM.
3) Supported returned value for lbr_fmt from above msr is non-zero.
4) Guest vcpu model does support FEAT_1_ECX.CPUID_EXT_PDCM.
5) User-provided lbr-fmt value doesn't violate its bitmask (0x3f).
6) Target guest LBR format matches that of host.
Co-developed-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-3-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 10 ++++++++++
2 files changed, 50 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6083e556f5..856a8659e8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6275,6 +6275,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
**errp)
CPUX86State *env = &cpu->env;
Error *local_err = NULL;
static bool ht_warned;
+ unsigned requested_lbr_fmt;
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
error_setg(errp, "apic-id property was not initialized properly");
@@ -6292,6 +6293,42 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
**errp)
goto out;
}
+ /*
+ * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
+ * with user-provided setting.
+ */
+ if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) {
+ if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) {
+ error_setg(errp, "invalid lbr-fmt");
+ return;
+ }
+ env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT;
+ env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt;
+ }
+
+ /*
+ * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
+ * 3)vPMU LBR format matches that of host setting.
+ */
+ requested_lbr_fmt =
+ env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT;
+ if (requested_lbr_fmt && kvm_enabled()) {
+ uint64_t host_perf_cap =
+ x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false);
+ unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT;
+
+ if (!cpu->enable_pmu) {
+ error_setg(errp, "vPMU: LBR is unsupported without pmu=on");
+ return;
+ }
+ if (requested_lbr_fmt != host_lbr_fmt) {
+ error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match "
+ "the host value (0x%x).",
+ requested_lbr_fmt, host_lbr_fmt);
+ return;
+ }
+ }
+
x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
@@ -6644,6 +6681,8 @@ static void x86_cpu_initfn(Object *obj)
object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
+ cpu->lbr_fmt = ~PERF_CAP_LBR_FMT;
+ object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt");
if (xcc->model) {
x86_cpu_load_model(cpu, xcc->model);
@@ -6798,6 +6837,7 @@ static Property x86_cpu_properties[] = {
#endif
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
+ DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
HYPERV_SPINLOCK_NEVER_NOTIFY),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9661f9fbd1..6730df5dbf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -386,6 +386,7 @@ typedef enum X86Seg {
#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
#define MSR_IA32_PERF_CAPABILITIES 0x345
+#define PERF_CAP_LBR_FMT 0x3f
#define MSR_IA32_TSX_CTRL 0x122
#define MSR_IA32_TSCDEADLINE 0x6e0
@@ -1810,6 +1811,15 @@ struct ArchCPU {
*/
bool enable_pmu;
+ /*
+ * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
+ * This can't be initialized with a default because it doesn't have
+ * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
+ * returned by kvm_arch_get_supported_msr_feature()(which depends on both
+ * host CPU and kernel capabilities) to the guest.
+ */
+ uint64_t lbr_fmt;
+
/* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
* disabled by default to avoid breaking migration between QEMU with
* different LMCE configurations.
--
2.36.0
- [PULL 00/23] Misc QEMU patches for 2022-05-16, Paolo Bonzini, 2022/05/16
- [PULL 01/23] WHPX: fixed TPR/CR8 translation issues affecting VM debugging, Paolo Bonzini, 2022/05/16
- [PULL 02/23] qga-vss: Add auto generated headers to dependencies, Paolo Bonzini, 2022/05/16
- [PULL 03/23] qga-vss: Use the proper operator to free memory, Paolo Bonzini, 2022/05/16
- [PULL 05/23] qdev-properties: Add a new macro with bitmask check for uint64_t property, Paolo Bonzini, 2022/05/16
- [PULL 04/23] i386/cpu: Remove the deprecated cpu model 'Icelake-Client', Paolo Bonzini, 2022/05/16
- [PULL 06/23] target/i386: Add lbr-fmt vPMU option to support guest LBR,
Paolo Bonzini <=
- [PULL 07/23] target/i386: Add kvm_get_one_msr helper, Paolo Bonzini, 2022/05/16
- [PULL 09/23] target/i386: Add XSAVES support for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 08/23] target/i386: Enable support for XSAVES based features, Paolo Bonzini, 2022/05/16
- [PULL 10/23] target/i386: Add MSR access interface for Arch LBR, Paolo Bonzini, 2022/05/16
- [PULL 11/23] target/i386: Enable Arch LBR migration states in vmstate, Paolo Bonzini, 2022/05/16
- [PULL 12/23] target/i386: introduce helper to access supported CPUID, Paolo Bonzini, 2022/05/16
- [PULL 13/23] target/i386: Support Arch LBR in CPUID enumeration, Paolo Bonzini, 2022/05/16
- [PULL 15/23] rng: make opened property read-only, Paolo Bonzini, 2022/05/16
- [PULL 16/23] soundhw: remove ability to create multiple soundcards, Paolo Bonzini, 2022/05/16
- [PULL 17/23] soundhw: extract soundhw help to a separate function, Paolo Bonzini, 2022/05/16