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[PULL 23/60] ppc/pnv: Subclass quad xscom callbacks
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 23/60] ppc/pnv: Subclass quad xscom callbacks |
Date: |
Fri, 7 Jul 2023 08:30:31 -0300 |
From: Joel Stanley <joel@jms.id.au>
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-ID: <20230704054204.168547-3-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv.c | 11 +++++++----
hw/ppc/pnv_core.c | 40 ++++++++++++++++++++++++++-------------
include/hw/ppc/pnv_core.h | 13 ++++++++++++-
3 files changed, 46 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index fc083173f3..c77fdb6747 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj)
}
static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
- PnvCore *pnv_core)
+ PnvCore *pnv_core,
+ const char *type)
{
char eq_name[32];
int core_id = CPU_CORE(pnv_core)->core_id;
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
+ sizeof(*eq), type,
&error_fatal, NULL);
object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
@@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error
**errp)
for (i = 0; i < chip9->nr_quads; i++) {
PnvQuad *eq = &chip9->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power9"));
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10, Error **errp)
for (i = 0; i < chip10->nr_quads; i++) {
PnvQuad *eq = &chip10->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power9"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0f451b3b6e..73d25409c9 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -407,12 +407,14 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
+ PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
char name[32];
snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
- &pnv_quad_power9_xscom_ops,
- eq, name, PNV9_XSCOM_EQ_SIZE);
+ pqc->xscom_ops,
+ eq, name,
+ pqc->xscom_size);
}
static Property pnv_quad_properties[] = {
@@ -420,6 +422,14 @@ static Property pnv_quad_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
+{
+ PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
+
+ pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
+ pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
+}
+
static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -429,16 +439,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void
*data)
dc->user_creatable = false;
}
-static const TypeInfo pnv_quad_info = {
- .name = TYPE_PNV_QUAD,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(PnvQuad),
- .class_init = pnv_quad_class_init,
+static const TypeInfo pnv_quad_infos[] = {
+ {
+ .name = TYPE_PNV_QUAD,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvQuad),
+ .class_size = sizeof(PnvQuadClass),
+ .class_init = pnv_quad_class_init,
+ .abstract = true,
+ },
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power9"),
+ .class_init = pnv_quad_power9_class_init,
+ },
};
-static void pnv_core_register_types(void)
-{
- type_register_static(&pnv_quad_info);
-}
-
-type_init(pnv_core_register_types)
+DEFINE_TYPES(pnv_quad_infos);
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 3d75706e95..77ef00f47a 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -60,8 +60,19 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
return (PnvCPUState *)cpu->machine_data;
}
+struct PnvQuadClass {
+ DeviceClass parent_class;
+
+ const MemoryRegionOps *xscom_ops;
+ uint64_t xscom_size;
+};
+
#define TYPE_PNV_QUAD "powernv-cpu-quad"
-OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
+
+#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
+#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
+
+OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
struct PnvQuad {
DeviceState parent_obj;
--
2.41.0
- [PULL 13/60] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup(), (continued)
- [PULL 13/60] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup(), Daniel Henrique Barboza, 2023/07/07
- [PULL 14/60] target/ppc: Move common check in exception handlers to a function, Daniel Henrique Barboza, 2023/07/07
- [PULL 15/60] target/ppc: Remove some more local CPUState variables only used once, Daniel Henrique Barboza, 2023/07/07
- [PULL 16/60] target/ppd: Remove unused define, Daniel Henrique Barboza, 2023/07/07
- [PULL 17/60] target/ppc: Get CPUState in one step, Daniel Henrique Barboza, 2023/07/07
- [PULL 18/60] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump, Daniel Henrique Barboza, 2023/07/07
- [PULL 19/60] pnv/xive2: Fix TIMA offset for indirect access, Daniel Henrique Barboza, 2023/07/07
- [PULL 20/60] pnv/xive: Add property on xive sources to define PQ state on reset, Daniel Henrique Barboza, 2023/07/07
- [PULL 21/60] pnv/psi: Initialize the PSIHB interrupts to match hardware, Daniel Henrique Barboza, 2023/07/07
- [PULL 22/60] ppc/pnv: quad xscom callbacks are P9 specific, Daniel Henrique Barboza, 2023/07/07
- [PULL 23/60] ppc/pnv: Subclass quad xscom callbacks,
Daniel Henrique Barboza <=
- [PULL 24/60] ppc/pnv: Add P10 quad xscom model, Daniel Henrique Barboza, 2023/07/07
- [PULL 25/60] ppc/pnv: Add P10 core xscom model, Daniel Henrique Barboza, 2023/07/07
- [PULL 26/60] ppc/pnv: Return zero for core thread state xscom, Daniel Henrique Barboza, 2023/07/07
- [PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages, Daniel Henrique Barboza, 2023/07/07
- [PULL 28/60] ppc/pegasos2: Add support for -initrd command line option, Daniel Henrique Barboza, 2023/07/07
- [PULL 29/60] pnv/xive: Print CPU target in all TIMA traces, Daniel Henrique Barboza, 2023/07/07
- [PULL 30/60] pnv/xive2: Always pass a presenter object when accessing the TIMA, Daniel Henrique Barboza, 2023/07/07
- [PULL 31/60] target/ppc: Add LPAR-per-core vs per-thread mode flag, Daniel Henrique Barboza, 2023/07/07
- [PULL 32/60] target/ppc: SMT support for the HID SPR, Daniel Henrique Barboza, 2023/07/07
- [PULL 33/60] ppc/pnv: SMT support for powernv, Daniel Henrique Barboza, 2023/07/07