Re: [PATCH 2/2] ppc/pnv: Fix pervasive topology calculation for P10

[Cédric Le Goater]

Hello Caleb,

On 2/27/24 15:48, Caleb Schlossin wrote:
> Pervasive topology(PIR) calculation for core, thread ID was
> wrong for big cores (SMT8). Fixing for P10.
>
> Based on: <20240123195005.8965-1-calebs@linux.vnet.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com>

Since the initial patch [1] is not merged yet, you can simply send a v2
with the update. There is still some time before soft freeze [2].

The Subject of this patch [PATCH 2/2] seems to refer to a series. Is
there a patch 1/2 ?

Thanks,

C.



[1] https://lore.kernel.org/all/20240123195005.8965-1-calebs@linux.vnet.ibm.com/
[2] https://wiki.qemu.org/Planning/9.0

> ---
>   hw/ppc/pnv.c | 15 +++++++++++++--
>   1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 2f53883916..aa5aba60b4 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1068,12 +1068,23 @@ static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t 
> core_id,
>       }
>   }
>   
> +/*
> + *    0:48  Reserved - Read as zeroes
> + *   49:52  Node ID
> + *   53:55  Chip ID
> + *   56     Reserved - Read as zero
> + *   57:59  Quad ID
> + *   60     Core Chiplet Pair ID
> + *   61:63  Thread/Core Chiplet ID t0-t2
> + *
> + * We only care about the lower bits. uint32_t is fine for the moment.
> + */
>   static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
>                                    uint32_t thread_id)
>   {
>       if (chip->nr_threads == 8) {
> -        return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
> -               (thread_id >> 1);
> +        return (chip->chip_id << 8) | ((core_id / 4) << 4) |
> +               ((core_id % 2) << 3) | thread_id;
>       } else {
>           return (chip->chip_id << 8) | (core_id << 2) | thread_id;
>       }