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Re: [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory lay
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From: |
Logan Gunthorpe |
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Subject: |
Re: [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing |
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Date: |
Wed, 21 Nov 2018 10:59:43 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Logan Gunthorpe <address@hidden>
> ---
> hw/riscv/virt.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2b38f89070..6b6fa39aaa 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -47,14 +47,14 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } virt_memmap[] = {
> - [VIRT_DEBUG] = { 0x0, 0x100 },
> - [VIRT_MROM] = { 0x1000, 0x11000 },
> - [VIRT_TEST] = { 0x100000, 0x1000 },
> - [VIRT_CLINT] = { 0x2000000, 0x10000 },
> - [VIRT_PLIC] = { 0xc000000, 0x4000000 },
> - [VIRT_UART0] = { 0x10000000, 0x100 },
> - [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
> - [VIRT_DRAM] = { 0x80000000, 0x0 },
> + [VIRT_DEBUG] = { 0x0, 0x100 },
> + [VIRT_MROM] = { 0x1000, 0x11000 },
> + [VIRT_TEST] = { 0x100000, 0x1000 },
> + [VIRT_CLINT] = { 0x2000000, 0x10000 },
> + [VIRT_PLIC] = { 0xc000000, 0x4000000 },
> + [VIRT_UART0] = { 0x10000000, 0x100 },
> + [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
> + [VIRT_DRAM] = { 0x80000000, 0x0 },
> };
>
> static uint64_t load_kernel(const char *kernel_filename)
>
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, (continued)
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, Logan Gunthorpe, 2018/11/21
[Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/11/21
[Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing,
Logan Gunthorpe <=
[Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21