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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X
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From: |
Logan Gunthorpe |
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Subject: |
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe |
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Date: |
Wed, 21 Nov 2018 12:08:56 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 2018-11-21 12:02 p.m., Alistair Francis wrote:
>> Ok, how do I stop bbl from editing the device tree? I have a kernel with
>> Xilinx PCI support but it fails initializing on that machine (see below).
>
> You should just be able to edit the source, grep for "microsemi".
Gross.
> Do you see the MicroSemi PCIe probe in your dmesg?
I do when I have a kernel with microsemi PCI Support (specifically the
one included in the bbl you sent us a while back).
>>
>>>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>>>> least explained in the commit message.
>>>
>>> What should we say? The QEMU machine accurately models the real
>>> hardware which reports a Xilinx PCIe. The confusion generally appears
>>> above QEMU where people are used to using the MicroSemi one.
>>
>> Maybe describing the bbl issue and what to do to overcome it would be
>> sufficient.
>
> This is not really a QEMU problem though. If you tried to use the
> Xilinx PCIe board on hardware you would see the same thing. Most
> people don't have a MicroSemi board so most aren't using bbl versions
> that are editing it into their device tree.
It's a qemu problem in that people will want to be able to actually use
qemu... somehow. It has to be documented what's required here. You can't
just say that the sifive_u machine won't work and it's someone else's
problem. People using qemu will not be able to figure out there are bbl
issues.
Logan
- Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, (continued)
- [Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/11/21
- [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing, Alistair Francis, 2018/11/21
- [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe,
Logan Gunthorpe <=
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21