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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe |
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Date: |
Wed, 21 Nov 2018 11:16:57 -0800 |
On Wed, Nov 21, 2018 at 11:09 AM Logan Gunthorpe <address@hidden> wrote:
>
>
>
> On 2018-11-21 12:02 p.m., Alistair Francis wrote:
> >> Ok, how do I stop bbl from editing the device tree? I have a kernel with
> >> Xilinx PCI support but it fails initializing on that machine (see below).
> >
> > You should just be able to edit the source, grep for "microsemi".
>
> Gross.
>
> > Do you see the MicroSemi PCIe probe in your dmesg?
>
> I do when I have a kernel with microsemi PCI Support (specifically the
> one included in the bbl you sent us a while back).
Yeah, so you need to make sure that doesn't happen.
They are practically the same device so they end up conflicting.
>
> >>
> >>>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> >>>> least explained in the commit message.
> >>>
> >>> What should we say? The QEMU machine accurately models the real
> >>> hardware which reports a Xilinx PCIe. The confusion generally appears
> >>> above QEMU where people are used to using the MicroSemi one.
> >>
> >> Maybe describing the bbl issue and what to do to overcome it would be
> >> sufficient.
> >
> > This is not really a QEMU problem though. If you tried to use the
> > Xilinx PCIe board on hardware you would see the same thing. Most
> > people don't have a MicroSemi board so most aren't using bbl versions
> > that are editing it into their device tree.
>
> It's a qemu problem in that people will want to be able to actually use
> qemu... somehow. It has to be documented what's required here. You can't
> just say that the sifive_u machine won't work and it's someone else's
> problem. People using qemu will not be able to figure out there are bbl
> issues.
I'm not saying the SiFive U won't work.
For people who have modified the standard bbl to edit the device tree
before passing it to Linux to add the MicroSemi PCIe node, it won't
work. That's a very small number of people who have modified the
standard boot loader. I don't think we need to document how those
people get back to the default set-up.
Alistair
>
> Logan
- [Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, (continued)
- [Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/11/21
- [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing, Alistair Francis, 2018/11/21
- [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe,
Alistair Francis <=
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21