[Discuss-gnuradio] Re: interfacing a DSP array card to USRP2

[Matt Ettus]

On 03/30/2010 11:48 AM, Jeff Brower wrote:
> Matt-
>
> We're working on a project at Signalogic to interface one of our DSP
> array PCIe cards to the USRP2.  This would provide a way for one or
> more TI DSPs to "insert" into the data flow and run C/C++ code for
> low-latency and/or other high performance applications.  The idea is
> that we would modify the current USRP2 driver (or create an
> alternative) so it would read/write to/from the PCIe card instead of
> the Linux (motherboard) GbE.
>
> A few general questions at this point:
>
> 1) We would connect the USRP2 to the GbE on our DSP array card.  We
> would want to shift latency/delay "downstream" to the PCIe card Linux
> driver interface, and make the GbE-to-GbE interface as low latency as
> possible.  Could you give us some guidance on which FPGA modules
> handle buffering for host transmit/receive?

The mac is all contained in simple_gemac, and above that in 
simple_gemac_wrapper:

http://code.ettus.com/redmine/ettus/projects/fpga/repository/revisions/master/show/usrp2/simple_gemac

which is instantiated in u2_core.  Most of the buffering happens in 
simple_gemac_wrapper in the fifo_2clock_cascade files.

> Is it reasonable we can
> reduce buffer sizes if the array card GbE has a fast response time?

You could drastically reduce this buffering if you could guarantee fast 
response.


> 2) We want to use the GNU radio GMAC as opposed to Xilinx or other
> off-the-shelf core, our thinking being that we can make contributions
> to data rate and latency-reduction discussions, as well as tech USRP2
> tech support, if we become familiar with your core.  Can you give us
> some guidance on a process to remove non-GMAC related modules from
> the firmware?  Go to the top level and start pulling?  Obviously SRAM
> related, CORDIC, and ADC/DAC interfaces, are not needed.

I would just start with the u2_core and simple_gemac_wrapper.  If you're 
not using the SERDES, that is a good place to start ripping out.

> 3) Do you have an FPGA internal achitecture block diagram of any
> type?  Is there another group you're aware of doing such "major
> modification" FPGA work that we might talk to?


There were some on the wiki at one time.  If they're not still there 
I'll post a talk I did which covers the architecture.


If you really just want high speed super low latency connections to 
another board, I would suggest using the SERDES (MIMO) interface 
instead.  It will have less latency than GbE.  You just need an FPGA 
with gigabit transceivers, or a TI TLK2701 chip to talk to.

Matt