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[PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
From: |
Philipp Tomsich |
Subject: |
[PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() |
Date: |
Sat, 4 Sep 2021 22:35:00 +0200 |
Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
regressions by introducing a temporary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v10:
- new patch
target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..c0a6e25826 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3)
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
{
- tcg_gen_ext32u_tl(arg1, arg1);
- tcg_gen_add_tl(ret, arg1, arg2);
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext32u_tl(t, arg1);
+ tcg_gen_add_tl(ret, t, arg2);
+ tcg_temp_free(t);
}
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
--
2.25.1
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), (continued)
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/05
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/05
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
[PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/04
[PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04
[PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/04
[PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(),
Philipp Tomsich <=
[PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/04
[PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/09/04
[PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/09/04