Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shif

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Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shif

From:	Richard Henderson
Subject:	Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Date:	Fri, 10 Sep 2021 15:40:26 +0200
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/10/21 3:36 PM, Philipp Tomsich wrote:

Richard,

Did you have a chance to consider what to do with clzw?
I would prefer to avoid the extra extension instructions and change the implementation(and would update the commit message to provide more context), but if you insist onsetting 'ctx->w' I'll just have the extra extensions emitted than delay this series further…

I don't mind not setting ctx->w, but bear in mind that UXL is going to automatically setthis flag when executing RV32 on RV64. That's why I have written a tcg patch set toeliminate unnecessary sign-extensions.

Do swap out EXT_ZERO for EXT_NONE in the gen_unary call if you're not going to make use ofany kind of source extension.

r~

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Re: [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, (continued)
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Bin Meng, 2021/09/08
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Bin Meng, 2021/09/08
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/05
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/05
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson <=
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
- [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Bin Meng, 2021/09/08
- [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04
- [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/04
- [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Richard Henderson, 2021/09/05
  - Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Alistair Francis, 2021/09/06
  - Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Bin Meng, 2021/09/08

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