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[PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-le
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From: |
Philipp Tomsich |
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Subject: |
[PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) |
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Date: |
Sat, 4 Sep 2021 22:35:02 +0200 |
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
bseti a2, zero, 63
addi a2, a2, 392
clzw a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).
Fix this by changing the implementation to:
1. shift the original register up by 32
2. performs a target-length (64bit) clz
3. return 32 if no bits are set
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v10:
- New patch, fixing correctnes for clzw called on a register with undefined
(as in: not properly sign-extended) upper bits.
target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 6c85c89f6d..8d29cadd20 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -349,8 +349,10 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_clzi_tl(ret, arg1, 64);
- tcg_gen_subi_tl(ret, ret, 32);
+ TCGv t = tcg_temp_new();
+ tcg_gen_shli_tl(t, arg1, 32);
+ tcg_gen_clzi_tl(ret, t, 32);
+ tcg_temp_free(t);
}
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
--
2.25.1
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, (continued)
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic),
Philipp Tomsich <=
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/05
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/05
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
[PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/04
[PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04
[PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/04