[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-ext
|
From: |
Bin Meng |
|
Subject: |
Re: [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension |
|
Date: |
Wed, 8 Sep 2021 13:22:52 +0800 |
On Sun, Sep 5, 2021 at 4:43 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The following instructions are part of Zbs:
> - b{set,clr,ext,inv}
> - b{set,clr,ext,inv}i
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and
> its use for qualifying the Zba instructions) are moved into a
> separate commit.
>
> target/riscv/insn32.decode | 17 +++++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
> 2 files changed, 24 insertions(+), 18 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/04
- [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/04
- [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- Re: [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension,
Bin Meng <=
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/04