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Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate o
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 |
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Date: |
Mon, 6 Sep 2021 15:45:32 +1000 |
On Sun, Sep 5, 2021 at 6:36 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The refactored gen_clzw() uses ret as its argument, instead of arg1.
> Fix it.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> Changes in v10:
> - New patch, fixing regressions discovered with x264_r.
>
> target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index c0a6e25826..6c85c89f6d 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3)
>
> static void gen_clzw(TCGv ret, TCGv arg1)
> {
> - tcg_gen_clzi_tl(ret, ret, 64);
> + tcg_gen_clzi_tl(ret, arg1, 64);
> tcg_gen_subi_tl(ret, ret, 32);
> }
>
> --
> 2.25.1
>
>
- [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/04
- [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/04
- [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04