[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate o
|
From: |
Bin Meng |
|
Subject: |
Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 |
|
Date: |
Wed, 8 Sep 2021 13:14:28 +0800 |
On Sun, Sep 5, 2021 at 4:35 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The refactored gen_clzw() uses ret as its argument, instead of arg1.
> Fix it.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - New patch, fixing regressions discovered with x264_r.
>
> target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/04
- [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/04
- [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04