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Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-ext
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension |
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Date: |
Wed, 8 Sep 2021 13:22:08 +0800 |
On Sun, Sep 5, 2021 at 4:38 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The following instructions are part of Zba:
> - add.uw (RV64 only)
> - sh[123]add (RV32 and RV64)
> - sh[123]add.uw (RV64-only)
> - slli.uw (RV64-only)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> Changes in v10:
> - Split off gen_add_uw() fix into a separate patch, as requested.
>
> Changes in v9:
> - Rebased to 8880cc4362.
> - Update gen_add_uw() to use a temporary instead of messing with
> arg1 (fixes a regression after rebase on CF3 and SPEC2017).
>
> Changes in v3:
> - The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro
> and its use for qualifying the Zba instructions) are moved into
> a separate commit.
>
> target/riscv/insn32.decode | 20 ++++++++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/04
- [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/04
- [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/04
- Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension,
Bin Meng <=
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04