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Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro |
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Date: |
Wed, 8 Sep 2021 13:25:35 +0800 |
On Sun, Sep 5, 2021 at 4:47 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> With the changes to Zb[abcs], there's some encodings that are
> different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
> we'll need a helper macro allowing us to select on RV32, as well.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Moved the REQUIRE_32BIT macro into a separate commit.
>
> target/riscv/translate.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, (continued)
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
- Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro,
Bin Meng <=
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/04
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/05
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/05
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
- Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
[PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/04
[PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04