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Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shif


From: Philipp Tomsich
Subject: Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Date: Fri, 10 Sep 2021 16:47:15 +0300


On Fri, 10 Sept 2021 at 16:40, Richard Henderson <richard.henderson@linaro.org> wrote:
On 9/10/21 3:36 PM, Philipp Tomsich wrote:
> Richard,
>
> Did you have a chance to consider what to do with clzw?
> I would prefer to avoid the extra extension instructions and change the implementation
> (and would update the commit message to provide more context), but if you insist on
> setting 'ctx->w' I'll just have the extra extensions emitted than delay this series further…

I don't mind not setting ctx->w, but bear in mind that UXL is going to automatically set
this flag when executing RV32 on RV64.  That's why I have written a tcg patch set to
eliminate unnecessary sign-extensions.

Ok, thanks!  Updated patches follow, once all test workloads have run…

Just wondering regarding the UXL-comment: the clzw instruction will be an illegal encoding for RV32 (the w-form instructions are present on RV64 only), so it should never be encountered in a RV32 instruction stream.  Did you mean that clz (the instruction operating on xlen-registers) would have ctx->w set for RV32 executing on RV64 ... or am I missing something fundamental?

Philipp.


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