Re: Add Verilog HDL syntax highlighting path

[Jorge Juan]

Hi Benno!

El jue, 7 ene 2021 a las 11:12, Benno Schulenberg
(<bensberg@telfort.nl>) escribió:
>
>
> Hello Jorge,
>
> Op 06-01-2021 om 21:03 schreef Jorge Juan:
> > I edit Verilog files frequently so I find it very useful to have
> > Verilog syntax highlighting in nano very useful. I hope you too.
>
> Thank you for posting the syntax.
>
> However, the "rule" for including a syntax into nano is that the files
> that the syntax is for can be found on an average GNU/Linux install.
> Verilog files are not among those.

Verilog coding in GNU/Linux is increasingly popular because starting a
few years ago we
have free software tools to do FPGA synthesis [1], so there exist a
complete toolchain
from Verilog description to actual chip implementation, not to mention
the very mature
Verilog simulators Icarus Verilog [2] and Verilator [3]. All these
tools are native GNU/Linux
tools and can be found pre-packaged in the most popular GNU/Linux distributions.

An average GNU/Linux install for a hardware developer (most CS
students take a course
on Verilog or VHDL design at some point) will include a Verilog
simulator, while the same
CS students will probably never need syntax highlighting for groff,
email or ocalm, all
included by default with nano. On the other hand, hardware people
(like myself) code
in Verilog more than in any other language.

>
> By the way, how does your syntax compare to the one posted on Savannah?
>   https://savannah.gnu.org/patch/download.php?file_id=40781
>   (from patch post https://savannah.gnu.org/patch/?9356)

I think the syntax configuration I propose is much cleaner and richer
than the previously
proposed in Savannah, which is more a work-in-progress proposal. The
one I propose is
quite in sync with the definition for C already in nano and includes
coloring for constants,
macros, numbers and operators, that the old proposal does not include.

The old proposal also include keywords for SystemVerilog, which is a
superset of Verilog. In my
opinion, a good syntax for SystemVerilog would require more work. I
may write one using
"extendsyntax", but since the use of SystemVerilog is still limited on
GNU/Linux systems
it is not as useful as plain Verilog at this point.

jorge.

>
[1] http://www.clifford.at/yosys/
[2] http://iverilog.icarus.com/
[3] https://www.veripool.org/

> Benno
>


-- 
Jorge Juan