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Re: add a Verilog HDL syntax highlighting file


From: ObeliX
Subject: Re: add a Verilog HDL syntax highlighting file
Date: Tue, 26 Jan 2021 18:14:32 +0100
User-agent: Mozilla/5.0 (X11; Linux i686; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

You have the long lines version already
there (they were just one commit away :)

yeez, stupid me. :)
I copied just the files and totally missed that there is a repository
with probably a whole history.


A historic revolution is taking place right now with all the new free
software toolchains for FPGA design that is spreading the use of
Verilog very quickly outside the professional world. Good times for
free software and open hardware!

in German industry VHDL is more prevalent. so I initially planned to
focus on VHDL. unfortunately the VHDL support in the open source
toolchains is missing or only very rudimentary. thus, I now learn
Verilog first. maybe it's even beneficial and as a C++ dev it's easier
for me to make progress.


thanx again :)

Obel



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