Re: add a Verilog HDL syntax highlighting file

[ObeliX]

> El dom, 10 ene 2021 a las 21:14, Jorge Juan (<jjchico@gmail.com>) escribió:
>
> Ok. Long regular expressions are now splitted in several lines. The
> number of regular expressions to parse has multiplied by 5 or 6
> (Verilog has lots of keywords) but who cares...
>
> I hope it helps.

hi Jorge,

would like to thank you for the Verilog syntax files. downloaded them
from your GitLab page. maybe you can add the 'very long lines'-version
there too?

by coincidence I bought a tinyFPGA-Bx just 3 weeks ago, to familiarize
myself with FPGAs and the IceStorm based open source toolchain for the
Lattice iCE40 devices. having syntax highlighting for it, is handy and
came just in the right moment. *thumpsup*


MfG Obel