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Re: add a Verilog HDL syntax highlighting file
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From: |
Jorge Juan |
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Subject: |
Re: add a Verilog HDL syntax highlighting file |
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Date: |
Tue, 26 Jan 2021 01:01:15 +0100 |
Hi ObeliX!
I am happy you find these Verilog syntax files useful. You have the
long lines version already there (they were just one commit away :)
The tinyFPGA-BX is really nice board: small and powerful. Also nice
(and free/open) is the Alhambra II from the FPGA-Wars team, with the
same family of chips and the Arduino pin-out.
A historic revolution is taking place right now with all the new free
software toolchains for FPGA design that is spreading the use of
Verilog very quickly outside the professional world. Good times for
free software and open hardware!
Cheers!
El mar, 26 ene 2021 a las 0:17, ObeliX (<ObeliX-@gmx.de>) escribió:
>
> > El dom, 10 ene 2021 a las 21:14, Jorge Juan (<jjchico@gmail.com>) escribió:
> >
> > Ok. Long regular expressions are now splitted in several lines. The
> > number of regular expressions to parse has multiplied by 5 or 6
> > (Verilog has lots of keywords) but who cares...
> >
> > I hope it helps.
>
> hi Jorge,
>
> would like to thank you for the Verilog syntax files. downloaded them
> from your GitLab page. maybe you can add the 'very long lines'-version
> there too?
>
> by coincidence I bought a tinyFPGA-Bx just 3 weeks ago, to familiarize
> myself with FPGAs and the IceStorm based open source toolchain for the
> Lattice iCE40 devices. having syntax highlighting for it, is handy and
> came just in the right moment. *thumpsup*
>
>
> MfG Obel
>
>
>
>
--
Jorge Juan-Chico
- Re: Add Verilog HDL syntax highlighting path, (continued)
- Re: Add Verilog HDL syntax highlighting path, Benno Schulenberg, 2021/01/07
- Re: Add Verilog HDL syntax highlighting path, Tomas Mudrunka, 2021/01/07
- Re: Add Verilog HDL syntax highlighting path, Jorge Juan, 2021/01/07
- Re: add a Verilog HDL syntax highlighting file, Benno Schulenberg, 2021/01/08
- Re: add a Verilog HDL syntax highlighting file, Jorge Juan, 2021/01/08
- Re: add a Verilog HDL syntax highlighting file, Jorge Juan, 2021/01/08
- Re: add a Verilog HDL syntax highlighting file, Benno Schulenberg, 2021/01/10
- Re: add a Verilog HDL syntax highlighting file, Jorge Juan, 2021/01/10
- Re: add a Verilog HDL syntax highlighting file, Jorge Juan, 2021/01/11
- Re: add a Verilog HDL syntax highlighting file, ObeliX, 2021/01/25
- Re: add a Verilog HDL syntax highlighting file,
Jorge Juan <=
- Re: add a Verilog HDL syntax highlighting file, ObeliX, 2021/01/26